Resume of David Whipp

NOTE: This is an outdated (historical record) of my resume. An up to date resume is available here.

Personal Details

Name: David Peter Whipp
Nationality: British (H1B Visa)
Date of Birth: 12 September 1970

Address: Santa Clara. CA.
Email: dave@whipp.name
Web: http://dave.whipp.name

Job Title: Senior Verification Engineer

In this job I lead our verification team and work to continuously enhance our methodology

The testbench is transaction-based, written in Perl using GreenLight's "Pivot", and connects to the design using Verilog BFMs. The tests are a combination of directed and random stimulus with result-checking accomplished using local assertions plus comparison against system-level C model. Nightly regressions use LSF over a server farm, with result tracking integrated with a web-based test-plan.
We enhanced an existing C-simulator from a sequential functional model to a transaction model, made cycle accurate with feedback from RTL. This novel methodology was the subject of my DesignCon2003 paper and presentation. I Initiated a UML/XML based modeling methodology for ongoing development of our golden models with RTL synchronization. The work was presented at the 2002 Shlaer-Mellor user group.
We successfully taped out 2 generations of our initial product, and are nearing completion of a companion chip. In my role as verification lead I have concentrated on both the correctness of the design of these products, and on the correctness of the specification from the perspective of usability by our customers and our internal bringup.

Porting & Productization of cycle level model (of uC core): we had a cycle precision golden model which we used for internal verification, on Unix. This golden model became a deliverable for customer use for high speed simulation on both Unix and NT platforms.
Performance modeling for branch prediction and cache configuration, including effects of multitasking: I wrote performance models and stimulated them with a trace-file splicer that emulated the effects of a multitasking kernel.
Verification (and specification) of FPU coprocessor: being involved from the start of the project, I was able to write a golden model of an FPU that co-evolved with the written specification.
Verification of Cache Controller in TriCore-based microcontroller: The cycle model and RTL were nearly complete, and a set of tests were required to verify these. I wrote a Perl based test generator that combined scenarios with data sets to produce self-checking TriCore assembler programs.
Regression system using LSF: realizing that the existing verification system was ad-hoc and becoming unusable, I wrote (c++) a flexible tool that automated the processes of running tests and regressions; and provided the ability to track and query the results of these regressions.

Testing of automotive microcontroller: memories and scan chains.

(Acquired by Mitel Semiconductor in Feb 1998; currently in business as Zarlink Semiconductor)

November 1997 - July 1998: ASIC Systems Embedded Systems Group: Hardware Design Engineer

Microcontroller System Testing (using C, ARM assembly and VHDL for test benches)
Tools for analysing test data, IAL-to-C Inverse Assembler Translator.

October 1996 - November 1997: ASIC Systems Embedded Systems Group, Systems Applications Engineer

April 1996 - October 1996: Microprocessor Business Unit

Macrocell Modeling using the Shlaer-Mellor method
PCMCIA Macrocell development - included integration of Leapfrog and SES Objectbench simulators
Software (Perl): Bus Slave generator

October 1993 - April 1996: CMOS Capability

"Experiences with RTL-Synchronized Transaction Reference Models": Paper and Presentation at DesignCon 2003
"Bottom-Up Modeling": Presentation at Shlaer-Mellor User Group Conference (SMUG'02)
"Constructing High Level Macrocell Models using the Shlaer-Mellor Method": Paper and Presentation at GPS Internal Technical Conference; Paper and Poster at European Solid State Circuits Conference (ESSCIRC'97)
"Splitting Domains and Constructing Bridges": Paper and Presentation at Shlaer-Mellor User Group Conference (SMUG'97)

First Class Honours degree of MEng in Microelectronic Systems Engineering.

IBM Prize for best managed final year project team.
Final year options: Parallel & Real Time Systems; Information Systems Modeling; Automated Synthesis Techniques for VLSI; Computer Vision Systems.
Final year project: A Domestic Equipment Display Reader for Blind People.

Transaction-Based testbenches: Greenlight's "Pivot": a Perl interface to Verilog PLI; Construction of BFMs using Verilog HDL (previously, VHDL); Exposure to SystemC, CynLib and TestBuilder C++ frameworks; Exposure to 'E' Language / Specman
Modeling: Functional and Transaction modeling in C and C++; Shlaer-Mellor OOA and RD; OOD with GOF patterns; UML notation; XML representation
Verification Infrastructure: Scripting using Perl (also other Unix tools); Techniques for fuzzy comparison of C-model Vs RTL simulations; Web-based systems for test-plan and regression result tracking; LSF and Condor job queuing systems; CVS, Continuus and Clearcase configuration management; GNATS bug-tracking system.
Miscellaneous: SES Objectbench and Aonix StP CASE Tools; Application and Applet progamming in Java (example); Z80, ARM, TriCore assembler programming; System V IPC and Sockets network programming; IAL (HP Logic Analyzer programming language); Abgen (Cadence layout manipulation tool)

Advanced Driving: I have an active interest in driver training and have taught Advanced Driving Techniques for improved road safety
Artificial Life & Artificial Intelligence: A long standing interest of mine has been the twin fields of artificial life and artificial intelligence. I selected a neural network project at University and have subsequently maintained an interest in this area. More recently, I have taken evening classes in psychology, to better understand the subject area.

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