Resume of David Whipp
April 2003 - Current: NVIDIA Corp, Santa Clara, CA.
Job Title: Verification Architect
At NVIDIA I enjoy a challenging role developing the framework, flows, and tools used by verification teams verifying our Graphics Processors (GPUs)
- Created, maintained, and supported a flexible unit verification environment that handles the diverse set of units found in a GPU, including support for legacy units and exploration of future flows. An important architectural consideration is the balance of diversity against the desire to standardize: promoting innovation while avoiding stagnation.
- "Agressive evolution" of in-house specification tool to enable detailed definition of the structure and interactions of design units (an example of an ESL tool). This includes a transaction level assertions library
- Maintained, supported, and evolved the simulation kernel of our transaction models. Whilst this is not yet SystemC, I have attempted to align our semantics with that standard while maintaining support for legacy models. Includes PLI cosim library that ensures stable event ordering across the interface irrespective of event ordering within the Verilog simulator.
- Created and supported PLI application to support context-switch testing methodology (including handling of deficiencies in different simulator and language versions)
- Created random assembly-level code generator to test video processing core
- Created SystemVerilog framework, on top of VMM, to take advantage of our ESL interface definition langauge.
- Verified (unit-level) MMU using graph-walking approach (using Breker's Trek) on top of our vmm testbench environment
- Created interactive coverage browser (using AJAX) as a front end to Synopsys URG reports.
November 2000 - March 2003: Fast-Chip, Sunnyvale. CA.
Verification Lead for Network Packet Classifier ASIC
Verification of TriCore: a hibrid CPU+DSP embedded core
- Created and maintained transaction-based testbench, written in Perl using GreenLight's "Pivot".
- Enhanced an existing C-simulator from a algorithmic model to a transaction model, made cycle accurate with feedback from RTL.
- Porting & productization of cycle level model (of uC core).
- Performance modeling for branch prediction and cache configuration.
- Verification of Cache Controller and FPU coprocessor.
- Created regression system using LSF
August 1998 - January 1999: Siemens AG, Munich, Germany.
- Testing of automotive microcontroller: memories and scan chains.
1989 - July 1998: GEC Plessey Semiconductor, Plymouth, UK.
- SOC methodology creation using ARM cores
- Microcell library characterization
Papers and Presentations
A full list of DV-related papers and presentations are here. Some highlights:
I have been chair of the Verification Track at DesignCon from 2004 to present.
- "Transaction Assertions in an Interface Definition Language"
- Paper and Presentation at DesignCon 2008 (link)
- "Traceability: from Transactions to RTL"
- Presentation at ICCAD06 (link)
- "A Multiparadigm Verification Flow"
- Paper and Presentation at DesignCon 2006 (link)
- "Experiences with RTL-Synchronized Transaction Reference Models"
- Paper and Presentation at DesignCon 2003 (link)
1989 - 1993: UMIST, Manchester
- First Class Honours degree of MEng in Microelectronic Systems Engineering.
Tools and Techniques
- Programming Languages
- C++ (including metatemplate programming)
- Perl (strong Perl5 coding, with good understanding of upcoming Perl6)
- Verilog and SystemVerilog (focus on testbench subset)
- UML (and its predecessors such as Shlaer-Mellor OOA -- paper)
- Verification Architecture
- Testbench architecture (including transaction assertions and coverage)
- ESL Methodology
- Object oriented design
- Architecture for reliable distributed build systems
- Metrics gathering and analyais
- Perforce, Clearcase, CVS, SCCS version control systems
- Non-trivial PLI programming (using VPI)
- Z80, ARM, TriCore assembler programming