Resume of David Whipp

Employment

Jan 2011 - Current: Google, Mountain View, CA.

Job Title: Software Engineer

At Google I enjoy a challenging role, leading projects in the areas of natural language understanding and dialog systems: part of the intersection of Googles Search and Android product areas.

As a 20% project, added intervals (error bars) to the Google Charts API.

April 2003 - Jan 2011: NVIDIA Corp, Santa Clara, CA.

Job Title: Verification Architect

At NVIDIA I enjoy a challenging role developing the framework, flows, and tools used by verification teams verifying our Graphics Processors (GPUs)

Prior to 2003

November 2000 - March 2003: Fast-Chip, Sunnyvale. CA.
Verification Lead for Network Packet Classifier ASIC
Created and maintained transaction-based testbench, written in Perl using GreenLight's "Pivot".
Enhanced an existing C-simulator from a algorithmic model to a transaction model, made cycle accurate with feedback from RTL.
January 1999 - October 2000: Infineon Technologies Corp. San Jose. CA.
Verification of TriCore: a hibrid CPU+DSP embedded core
Porting & productization of cycle level model (of uC core).
Performance modeling for branch prediction and cache configuration.
Verification of Cache Controller and FPU coprocessor.
August 1998 - January 1999: Siemens AG, Munich, Germany.
Testing of automotive microcontroller: memories and scan chains.
1989 - July 1998: GEC Plessey Semiconductor, Plymouth, UK.
SOC methodology using ARM cores
Microcell library characterization

Papers and Presentations

A full list of DV-related papers and presentations are here. Some highlights:
"Transaction Assertions in an Interface Definition Language"
Paper and Presentation at DesignCon 2008 (link)
"Traceability: from Transactions to RTL"
Presentation at ICCAD06 (link)
"A Multiparadigm Verification Flow"
Paper and Presentation at DesignCon 2006 (link)
"Experiences with RTL-Synchronized Transaction Reference Models"
Paper and Presentation at DesignCon 2003 (link)
Working on the field of Design Verification, I chaired the Verification Track at DesignCon from 2004 to 2011.

Education

1989 - 1993: UMIST, Manchester

Tools and Techniques

Software Engineering and Management
Strong coding skills (recently, mostly C++, Python, and Javascript).
Maintaining code quailty through code reviews and design discussions.
Mentoring and coaching: understanding how to give feedback in differing situations.
Programming Languages (maybe a little rusty on some)
C++ (including metatemplate programming)
Perl (strong Perl5 coding, with good understanding of upcoming Perl6)
Verilog and SystemVerilog (focus on testbench subset)
Javascript, Java, SQL, PHP, and related web technologies
ARM, Z80 assembly languages
ASIC Design Verification Architecture
Testbench architecture (including transaction assertions and coverage)
ESL Methodology
Object oriented design
Architecture for reliable distributed build systems
Metrics gathering and analyais


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