Dave Whipp's ASIC Design Verification Pages

Verification of modern ASIC designs is a complex process, and is often cited as a bottlenect in the ASIC design process. This is largely because the designs of the ASICs are, themselves, getting ever more complex; but I believe that the main cause of the verificatiuon bottleneck is the methodology that underpins it. Even today, many managers believe that we should still apply the principles that were developed when the size of the chips was measured in millions of transistors, not billions. Todays ASICs are akin to medium scale software sytems.

My first job in HW verification was as a summer intern in 1990. This followed my first year at UMIST (now Univerity of Manchester) studying for my degree in Microelectronic Systems Engineering. Twenty years later, in January 2011, I moved to Google to work as a Software Engineer. Testing is a signifiant part of my role there, but software testing and hardware verification are suprisingly different beasts.

Papers

These are papers I've presented over the years. Most have been presented at DesignCon. Although the audiences can be fairly small there, I like the ability to fully explore a subject in their 40 minute presentations.

Exploiting "Architecture for Verification" to Streamline the Verification Process: my paper (with slides) for special session at DAC09.
Transaction Assertions in an Interface Definition Language: my paper (with slides) at DesignCon 2008.
"A Multiparadigm Verification Flow": DesignCon2006 paper (with slides), A discussion on the need for, and implementation of, verification flows that support diversity.
An update of my 2003 paper, for DesignCon East later that same year
RTL-Synchronized Transaction Reference Models: my paper (with slides) at DesignCon 2003.
My first published paper, from 1997: Constructing Macrocell Models using the Shlaer-Mellor Method

Other Stuff

Various writings and presentations, which are less rigorous that full papers. You might also be interested in my software pages.

My parting thoughts as a verification engineer, posted to Verification Guild in February 2011.
My talk for DVClub, August 2008.
An Interview for SCDsource on the verification of the GeForce 8800.
Introspection in System Verilog. A quick note of how to call VPI fuctions using DPI from within SystemVerilog source code.
"The Functional Verification of Electronic Systems". This book, edited by Brian Bailey, contains much wisdom in the field of verification from a number of authors. My contribution is Chapter 6.
Traceability: From Transactions to RTL -- presentation at ICCAD06
Verification using Parrot: a new virtual machine for dynamic languages
Some thoughts on the levels of abstraction in ASIC verification
Slides and notes from my DesignCon2004 panel discussion
My initial thoughts when I first created this page.

Verification Links

DV Club an organisation where Verification Engineers meet for a lunch and to listen to a talk.
Link to Mike Mintz's verification pages: trusster.com.
Janick Bergeron's Verification Guild
GreenLight LLC: home of Pivot, a testbench (Verilog PLI) module for Perl
SystemC: a modeling class-library for C++

As I said above, this is in a state of constant (but fairly low frequency) change. I always welcome any suggestions for content (or style, or whatever) you may have: some of the posts I reference above are a direct result of questions people have asked me either by email or when we met at conferences. My public email address is dave@whipp.name (be aware that public email addresses can have harsh spam filters -- use a subject that begins "DV:" to be safe)

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