Dave Whipp's ASIC Design Verification Pages

Verification of modern ASIC designs is a complex process, and is often cited as a bottlenect in the ASIC design process. This is largely because the designs of the ASICs are, themselves, getting ever more complex; but I believe that the main cause of the verificatiuon bottleneck is the methodology that underpins it. Even today, many managers believe that we should still apply the principles that were developed when the size of the chips was measured in millions of transistors, not billions. Todays ASICs are akin to medium scale software sytems.

My first job in HW verification was as a summer intern in 1990. This followed my first year at UMIST (now Univerity of Manchester) studying for my degree in Microelectronic Systems Engineering. Twenty years later, in January 2011, I moved to Google to work as a Software Engineer. Testing is a signifiant part of my role there, but software testing and hardware verification are suprisingly different beasts.


These are papers I've presented over the years. Most have been presented at DesignCon. Although the audiences can be fairly small there, I like the ability to fully explore a subject in their 40 minute presentations.

Other Stuff

Various writings and presentations, which are less rigorous that full papers. You might also be interested in my software pages.

Verification Links

As I said above, this is in a state of constant (but fairly low frequency) change. I always welcome any suggestions for content (or style, or whatever) you may have: some of the posts I reference above are a direct result of questions people have asked me either by email or when we met at conferences. My public email address is dave@whipp.name (be aware that public email addresses can have harsh spam filters -- use a subject that begins "DV:" to be safe)