Previous Resume of David Whipp
Note: This document is historical: I have kept it as a memory. My current resume is available here
November 2000 - current: Fast-Chip, Sunnyvale. CA.
Job Title: Senior Verification Engineer
In this job I have lead our verification team in the evolution our verification capability.
- Took over responsibility for verification infrastructure: a C-simulator vs RTL system. Made numerous enhancements to our test-script language and testbench BFMs/monitors. Coordinated the work of other team members for the evolution of the infrastructure.
- Enhanced existing C-simulator from a sequential functional model to a transaction oriented model that is capable of duplicating the full parallel behaviour of the hardware. Other team members are now using this framework when adding new features.
- Initiated a UML/XML based modeling methodology for ongoing development of our golden models. (Note: this is a long term interest of mine: any future employment should enable me to continue researching better ways of building models)
- Porting & Productization of cycle level model (of uC core): we had a cycle precision golden model which we used for internal verification, on Unix. This golden model became a deliverable for customer use for high speed simulation on both Unix and NT platforms. Production of a verified common code base (including build process) that produces the model as a DLL for NT and a lib.so for Unix.
- Performance modelling for branch prediction and cache configuration, including effects of multitasking: Most benchmarks look at performance for a specific type of application. The purpose of TriCore is to allow DSP and C-style processes to run on a single core. I wrote performance models and stimulated them with a trace-file splicer that emulated the effects of a multitasking kernel.
- Verification (and specification) of FPU coprocessor: being involved from the start of the project, I was able to write a golden model of an FPU that co-evolved with the written specification. The aim of the FPU was to act as a hardware accelerator for the software IEEE library -- the FPU itself did not need to be compliant. The model was used to optimise the interface between the hardware and software: the aim was to optimise the assembler code within a specific hardware budget. The model was later evolved into the reference model for RTL verification.
- Verification of Cache Controller in Tricore-based microcontroller: The cycle model and RTL were nearly complete, and a set of tests were required to verify these. I wrote a Perl based test generator that combined scenarios with data sets to produce self-checking TriCore assembler programs (The Perl included the expected-result generator to enable it to generator the code that checked the results).
- Set up regression system using LSF: realising that the existing verification system was ad-hoc and becoming unusable, I wrote (c++) a flexible tool to manage the process of running tests and regressions. It maintains an audit trail, distributes simulations (and test-generation) using LSF, optimises Leapfrog simulations (eliminates startup time for most tests) and provides a powerful query mechanism for viewing results. In addition it can be used to recreate failed tests for debug.
August 1998 - January 1999: Siemens AG, Munich, Germany.
Worked on testing of automotive microcontroller: memories and scan chains.
1989 - July 1998: Mitel Semiconductor, Plymouth, UK.
(February 1998: Mitel acquired GEC Plessey Semiconductors)
November 1997 - July 1998: ASIC Systems Embedded Systems Group: Hardware Design Engineer
October 1996 - November 1997: ASIC Systems Embedded Systems Group, Systems Applications Engineer
- Microcontroller System Testing (using C, ARM assembly and VHDL for test benches)
- Tools for analysing test data, IAL-to-C Inverse Assembler Translator.
April 1996 - October 1996: Microprocessor Business Unit
- Support for ARM based microcontrollers
- Software (IAL): HP Logic Analyser Inverse Assembler
October 1993 - April 1996: CMOS Capability
- Macrocell Modelling using the Shlaer-Mellor method
- PCMCIA Macrocell development - included integration of Leapfrog and SES Objectbench simulators
- Software (Perl): Bus Slave generator
1989 - 1993: Sponsored Student
- Layout Abstract Generation (Cadence Skill, Abgen)
- Automated Microcell Characterisation Software (C, Lex/Yacc; Spectre simulator)
- Implementation of ERC (Electrical Rules Checks) Software
- Design Library Management Software (tcl, C, xdr (Sun RPC))
- Student and graduate training schemes
1989 - 1993: UMIST, Manchester
First Class Honours degree of MEng in Microelectronic Systems Engineering.
- IBM Prize for best managed final year project team.
- Final year options: Parallel & Real Time Systems; Information Systems Modelling; Automated Synthesis Techniques for VLSI; Computer Vision Systems.
- Final year project: A Domestic Equipment Display Reader for Blind People.
1982 - 1989: The Wallasey School, Wirral
- 'A' Levels (1989): Maths (A), Further Maths (B), Physics (B), Chemistry (B), General Studies (B).
- 'AO' Levels (1988): Maths (A), General Paper (C).
- 'O' Levels (1987): English Language (A), Maths (A), Physics (A), Control technology (A), Computer Studies (A), Chemistry (B), History (C), Art (C)
Papers and Presentations
- "Experiences with RTL-Synchronized Transaction Reference Models"
- Paper and Presentation at DesignCon 2003
- "Bottom-Up Modeling"
- Presentation at Shlaer-Mellor User Group Conference (SMUG'02)
- "Constructing High Level Macrocell Models using the Shaler-Mellor Method"
- Paper and Presentation at GPS Internal Technical Conference
- Paper and Poster at European Solid State Circuits Conference (ESSCIRC'97)
- "Splitting Domains and Constructing Bridges"
- Paper and Presentation at Shlaer-Mellor User Group Conference (SMUG'97)
Tools and Techniques
- System Modeling
- Shlaer-Mellor OOA and RD
- OOD with GOF patterns; UML notation
- SES Objectbench and Aonix StP CASE Tools
- 'E' Language / Specman
- General Software Implementation
- C, C++, Perl, Java. Fifos and Sockets.
- Embedded Software Implementation
- C, ARM Assembler, Tricore Assembler
- HP Logic Analyser
- Hardware Description Languages
- VHDL and Verilog.
- Greenlight's "Pivot" perl interface to vlog PLI
- Exposure to SystemC, CynLib and TestBuilder C++ frameworks
- Perl, Tcl, Sed/Awk, csh. Skill (Cadence)
- Internet Programming
- HTML, Java, CGI, XML
- IAL (HP Logic Analyser programming language)
- Abgen (Cadence layout manipulation tool)
- System V IPC and network programming
- LSF and Condor job queuing systems
- CVS, Continuus and Clearcase configuration management
- MS Office, FrameMaker, Visio
- Advanced Driving
- I have an active interest in driver training and teach Advanced Driving Techniques for improved road safety
- An interesting counterpoint to solid computation; I took evening classes in the subject (gaining grade A GCSE)
- Artificial Life & Artificial Intelligence
- A long standing interest of mine has been the twin fields of artificial life and artificial intelligence. I selected a neural network project at University and have subsequently maintained an interest in this area.
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