Previous Resume of David Whipp

Note: This document is historical: I have kept it as a memory. My current resume is available here

Personal Details

Name: David Peter Whipp
Nationality: British (H1B Visa)
Address: Santa Clara. CA.


November 2000 - current: Fast-Chip, Sunnyvale. CA.

Job Title: Senior Verification Engineer

In this job I have lead our verification team in the evolution our verification capability.

January 1999 - October 2000: Infineon Technologies Corp. San Jose. CA.

August 1998 - January 1999: Siemens AG, Munich, Germany.

Worked on testing of automotive microcontroller: memories and scan chains.

1989 - July 1998: Mitel Semiconductor, Plymouth, UK.

(February 1998: Mitel acquired GEC Plessey Semiconductors)

November 1997 - July 1998: ASIC Systems Embedded Systems Group: Hardware Design Engineer

October 1996 - November 1997: ASIC Systems Embedded Systems Group, Systems Applications Engineer April 1996 - October 1996: Microprocessor Business Unit October 1993 - April 1996: CMOS Capability 1989 - 1993: Sponsored Student


1989 - 1993: UMIST, Manchester

First Class Honours degree of MEng in Microelectronic Systems Engineering.

1982 - 1989: The Wallasey School, Wirral

Papers and Presentations

"Experiences with RTL-Synchronized Transaction Reference Models"
Paper and Presentation at DesignCon 2003
"Bottom-Up Modeling"
Presentation at Shlaer-Mellor User Group Conference (SMUG'02)
"Constructing High Level Macrocell Models using the Shaler-Mellor Method"
Paper and Presentation at GPS Internal Technical Conference
Paper and Poster at European Solid State Circuits Conference (ESSCIRC'97)
"Splitting Domains and Constructing Bridges"
Paper and Presentation at Shlaer-Mellor User Group Conference (SMUG'97)

Tools and Techniques

System Modeling
Shlaer-Mellor OOA and RD
OOD with GOF patterns; UML notation
SES Objectbench and Aonix StP CASE Tools
'E' Language / Specman
General Software Implementation
C, C++, Perl, Java. Fifos and Sockets.
Embedded Software Implementation
C, ARM Assembler, Tricore Assembler
HP Logic Analyser
Hardware Description Languages
VHDL and Verilog.
Greenlight's "Pivot" perl interface to vlog PLI
Exposure to SystemC, CynLib and TestBuilder C++ frameworks
Perl, Tcl, Sed/Awk, csh. Skill (Cadence)
Internet Programming
IAL (HP Logic Analyser programming language)
Abgen (Cadence layout manipulation tool)
System V IPC and network programming
LSF and Condor job queuing systems
CVS, Continuus and Clearcase configuration management
MS Office, FrameMaker, Visio


Advanced Driving
I have an active interest in driver training and teach Advanced Driving Techniques for improved road safety
An interesting counterpoint to solid computation; I took evening classes in the subject (gaining grade A GCSE)
Artificial Life & Artificial Intelligence
A long standing interest of mine has been the twin fields of artificial life and artificial intelligence. I selected a neural network project at University and have subsequently maintained an interest in this area.

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